Understand how each chip is built and connected
This page is the entry point for architecture-first chip profiles. It is designed to bring together topology diagrams, external interface definitions, port counts, bandwidth classes, and other hardware capability details that do not fit inside a simple spec table.
Architecture Diagrams
High-level block diagrams for compute clusters, memory hierarchy, interconnect topology, and accelerator packaging.
External Interfaces
PCIe, NVLink, Ethernet, SerDes, MIPI, camera, display, and host I/O definitions with version and lane-level detail.
Interface Counts
How many links, ports, memory channels, and accelerator-facing interfaces each chip exposes in real deployments.
Capability Notes
Bandwidth ceilings, memory capacity envelope, media engines, virtualization support, and platform constraints.
Architecture Cards
Each chip now has an architecture entry card. Open a card to view the new architecture detail skeleton, then extend it later with block diagrams, interface matrices, and vendor-specific capability notes.
Cloud Architecture
Server accelerators, expansion fabrics, and memory-topology oriented parts.
Edge Architecture
Embedded AI SoCs, sensor-facing platforms, and low-power deployment targets.
What each architecture profile will include
Architecture diagram and subsystem overview
Detailed external interface definitions and supported protocols
Interface count, lane width, and bandwidth notes
Memory connectivity, packaging, and expansion constraints
Media, security, virtualization, and deployment capability notes
Start from a chip family, then open the hardware detail
The long-term plan is to connect cloud and edge chip entries to architecture profiles, so users can move from summary specs into concrete hardware design, interface detail, and deployment constraints.